tc4x SOTA
寄存器
SMM_STMEM1
(SMM 0xF0060000 + 0x00C8H)
Start-up Memory Register 1
| Field | Bits | Type | Description |
|---|---|---|---|
| BIDX | [12:11] | rw | Index of the valid BMHD |
| SCFG | [18:17] | rw | 0: no SWAP configured by SSW 01: SWAP A configured (address region A active, B inactive). 10: SWAP B configured (address region B active, A inactive) |
| ST | [19] | rw | 0: SWAP configuration done based on UCB_SWAP_ORIG 1: SWAP configuration done based on UCB_SWAP_COPY |
| SIDX | [26:20] | rw | Index x of SWAP entry in UCB_SWAP_ORIG/COPY containing valid marker |
UCB_RTC_USERCFG_ORIG
| Register | Bits | offset | Description |
|---|---|---|---|
| UCB0_17_SAL | [31:0] | 0x8800+0x0 | System address of this location |
| UCB0_17_LSENA | [5:1] | 0x8800+0x04 | Lockstep handling during start-up for CPUx(1:enable) |
| UCB0_17_RESERVED_1 | [31:0] | 0x8800+0x08 | – |
| UCB0_SMM_EXTIF_ESR0CNTCTRL | [31:0] | 0x8800+0x0C | SMM_ESR0CNTCTRL user configuration value |
| UCB0_PMS_PAD_ESR2CON | [31:0] | 0x8800+0x10 | PAD_ESR2CON user configuration value |
| UCB0_RAMINIT | [] | 0x8800+0x14 | rtc sram(warm power-on/cold power-on), cpux sram, cpux dlmu sram |
| UCB0_LBISTEXE | [31:0] | 0x8800+0x18 | LBIST check |
| UCB0_HOSTRAMAIN | [1:0] | 0x8800+0x1C | HOST SRAMs auto-initialization |
| UCB0_SWAP_ena | [3:0] | 0x8800+0x20 | SWAP activation enable:1010 disenable:0101 |
| UCB0_ADDRR_ena | [3:0] | 0x8800+0x24 | Device selection for address routing |
| CRC_RTCUSERCFGO1 | [31:0] | 0x8800+0x28 | crc(all above) |
| UCB0_17_PW0-7 | [31:0] | 0x8800+0x7D0-0x7EC | 256-bit password protection |
| UCB0_17_CONFIRMATION | [31:0] | 0x8800+0x7F0 | ERRORED UNLOCKED: 0x43211234 CONFIRMED: 0x57B5327F |
UCB_RTC_USERCFG_ORIG
(0xAE409000)
UCB_RTC_SWAP_ORIG
(0xAE409800U) x: [0-31] https://crccalc.com/?crc=AE40981043211234000000AA&method=CRC-32/ISO-HDLC&datatype=hex&outtype=hex
| Register | Bits | offset | Description |
|---|---|---|---|
| SWAP_ORIG_SAL x | [31:0] | 0x9800+x*0x10 | System address of this location |
| SWAP_ORIG_STATUS x | [31:0] | 0x9804+x*0x10 | VALID: 43211234 INVALID: 57B5327F |
| SWAP_ORIG_MARKER x | [31:0] | 0x9808+x*0x10 | linear or SOTA_A：0x55 SOTA_B：0xAA Invalid: else val |
| SWAP_ORIG_CRCSE x | [31:0] | 0x9800+x*0x10 | Crc: (SALx, STATUSx, MARKERx) |
| UCB0_19_PW0-7 | [31:0] | 0x9800+0x7D0-0x7EC | 256-bit password protection |
| UCB0_19_CONFIRMATION | [31:0] | 0x9800+0x7F0 | ERRORED UNLOCKED: 0x43211234 CONFIRMED: 0x57B5327F |
UCB_RTC_SWAP_COPY
(0xAE40A000U)
HCI_ERR
(0xF8040000u + 0x0010)
HOST command interface error register
| Field | Bits | Type | Description |
|---|---|---|---|
| ADER | [0] | rh | SRI bus Address error |
| SQER | [1] | rh | Command sequence error |
| PROER | [2] | rh | Protection error |
| ABER | [4] | rh | Abort error |
| CLER | [5] | rh | Clear error |
| PVER | [6] | rh | Program verify error |
| EVER | [7] | rh | Erase verify error |
| OPER | [16] | rh | Flash operation error |
| ORIER | [17] | rh | Original error |
DMU.GP_HOST_CONFIRMB
(0xF8040000u + 0x0534)
HOST UCB confirmation codes register B
| Field | Bits | Type | Description |
|---|---|---|---|
| PROINUSERCFGO | [1:0] | rh | UCB_RTC_USERCFG_ORIG confirmation state |
| PROINSWAPO | [3:2] | rh | UCB_RTC_SWAP_ORIG confirmation state |
| PROINFLASHO | [5:4] | rh | UCB_RTC_FLASH_ORIG confirmation state |
| PROINECPRIOO | [7:6] | rh | UCB_RTC_ECPRIO_ORIG confirmation state |
| PROINUSERCFGC | [17:16] | rh | UCB_RTC_USERCFG_COPY confirmation state |
| PROINSWAPC | [19:18] | rh | UCB_RTC_SWAP_COPY confirmation state |
| PROINFLASHC | [21:20] | rh | UCB_RTC_FLASH_COPY confirmation state |
| PROINECPRIOC | [23:22] | rh | UCB_RTC_ECPRIO_COPY confirmation state |
FAQ
SOTA memmap
- 写入：实际的物理地址
- 读取：虚拟的线性地址
PFLASH erase read ecc error
- Class 4， TIN 2
- 擦除之后dissable ecc，才能正常读取到 0
- ref： 6.3.14.2.2 PFLASH read configuration protection
1MODULE_PFRWB5B.UR.FLASHCON2.B.ECCCORDIS = 1;
2MODULE_PFRWB5B.UR.FLASHCON2.B.MASKUECC = 1;
3MODULE_PFRWB5B.UR.FLASHCON2.B.TDISUDATA = 1;
评论